As illustrated in FIG. 1, a conventional circuit for clamping the /RAS ("/" means bar) signals includes: VBB sensor 1 for detecting whether the voltage produced during the generation of a back bias voltage (VBB) has reached the desired level; transistor (MP1) 3 and ring oscillator 2 for driving charge pump 4 until the desired VBB level is reached; inverter 6 and latch circuit 5 for preventing the driving of NOR circuit 7; NOR circuit 7 maintains the clock on signal "LOW" during the initial period of setting up the VBB, and NOR circuit 7 transmits the clock-on signal in response to the /RAS signal after the VBB has been initially set up.
Latch circuit 5 includes two NOR gates, NOR1 and NOR2, to receive signals from VBB sensor 1 and power-up generator 8, and NOR circuit 7 receives the /RAS signal and the output of inverter 6.
NOR circuit 7 comprises two PMOS transistors, MP2, MP3, and two NMOS transistors, MN1, MN2. The MP2, MP3 and MN2 transistors are serially connected between power VDD and VSS. The gates of transistors MP3 and MN2 are commonly connected and are supplied with the /RAS signal. The gates of transistors MP2 and MN1 are commonly connected and are supplied with an inverted output of latch circuit 5. The drains and sources of transistors MN1 and MN2 are connected with each other and the clock on signal is output from a contact of the drains.
Once the power source is supplied, the S2 signal is produced by the power-up generator as illustrated in FIG. 2, while the S1 signal which is the output of VBB sensor 1 is maintained at a low level until the back bias voltage VBB reaches the desired level. Since node C is maintained at a high level during this period, even if the /RAS signal falls to a low level, the /RAS signal cannot be supplied to the chip, so that the clock-on signal is continuously maintained at a low level.
Meanwhile, when the VBB signal reaches the desired level, the S1 signal is shifted to a high level by VBB sensor 1, and, accordingly, the levels of nodes A, B and C are inverted by the S1 signal. The levels of the nodes A, B and C are maintained "low", "high" and "low," respectively. Thereby, the input of the /RAS signal is transferred to the chip as a clock-on signal.
In this conventional /RAS clamping circuit, even if the VBB voltage reaches the desired level during the initial chip set-up, the sense amplifiers can malfunction upon supplying the /RAS signal, as long as the bit line pre-charge voltage has not reached a 1/2 VDD level.
Further, memory chips are being improved into larger scale devices. As the bit line loading capacitance is increased in accordance with an increase in the memory capacity, a longer time is needed to set up all of the bit lines with a bit line pre-charge voltage. Thus, malfunctions of the sense amplifiers can occur, which are caused by the supply of the /RAS signal before the set-up of the VBLP voltage. Such malfunctions degrade the reliability of the semiconductor memory devices.